(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method of fabricating a metal oxide semiconductor field effect transistor (MOSFET) device, using a replacement gate dielectric layer and featuring spike rapid thermal oxidation procedures to preserve ultra-shallow junctions.
(2) Description of Prior Art
Miro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features needed to increase device performance and to reduce processing costs, has been in part accomplished via advancements in specific fabrication disciplines such as photolithography and dry etching. The use of more sophisticated exposure tools as well as the use of more sensitive photoresist materials have allowed sub-0.13 um features to be routinely defined in photoresist layers. In addition the development of more advanced dry etching tools and processes have allowed the sub-0.13 um features in masking photoresist shapes to be successfully transferred to underlying materials, such as the insulator, metal, and semiconductor layers, used for formation of semiconductor devices. However in addition to the shrinking features used for sub-0.13 um devices, the thickness of specific materials or elements of the sub-0.13 um device also have to be reduced. One such MOSFET element needed to be reduced in thickness to provide performance benefits is the gate dielectric layer, however the use of the thinner gate dielectric layers highlight specific areas of concern not as critical with the use of thicker gate dielectric layers. First, plasma induced damage of the gate dielectric layer, incurred during a plasma dry etching procedure used to define an overlying conductive gate structure, can result in deleterious charge generation in the underlying gate dielectric layer, in addition to degrading the gate dielectric breakdown strength. Secondly, when a gate dielectric layer such as silicon dioxide is formed on an underlying semiconductor alloy layer such as silicon-germanium, subsequent high temperature processing procedures can result in unwanted segregation of germanium at the silicon dioxide/silicon-germanium interface.
The present invention will describe a method of fabricating a MOSFET device wherein the conductive gate structure, formed on an underlying gate dielectric layer, is not defined via plasma dry etching procedures thus eliminating the possibility of plasma induced damage of the gate dielectric layer. In addition this invention will describe procedures used for the formation of the gate dielectric layer which also provide for activation of dopants in already formed ultra-shallow source/drain regions, thus eliminating the use of higher temperature dopant activation procedures, and thus allowing the use of silicon-germanium underlying the gate dielectric layer with decreased risk of germanium segregation phenomena. Prior art such as Buynoski et at, in U.S. Pat. No. 6,300,203 B1, Gardner et al, in U.S. Pat. No. 6,140,688, Lee et al, in U.S. Pat. No. 6,107,140, Kim, in U.S. Pat. No. 6,365,450 B1, Lee, in U.S. Pat. No. 6,391,697 B2, and Huang et al, in U.S. Pat. No. 6,033,963, describe methods of forming gate dielectric layers without subsequent exposure to plasma dry etching procedures. None of the above prior art however describe the novel combination of process steps used in the present invention featuring formation of a gate dielectric layer on a semiconductor alloy layer, without gate dielectric layer exposure to plasma dry etching procedures, and with a gate dielectric formation procedure allowing dopant activation to occur without segregation of a semiconductor alloy component at the gate dielectric-semiconductor alloy interface.
It is an object of this invention to fabricate a metal oxide semiconductor field effect transistor (MOSFET) device, wherein a gate insulator layer is formed on a semiconductor alloy layer.
It is another object of this invention to form a gate insulator layer via a multiple spike rapid thermal oxidation procedure, at temperatures which does not result in movement of dopants in already formed source/drain extension (SDE), regions.
It is still another object of this invention to define a conductive gate structure on an underlying gate insulator layer without the use of reactive ion etching (RIE) procedures, thus avoiding plasma induced damage (PID) of the gate insulator layer.
In accordance with the present invention a method of forming a MOSFET device featuring a gate insulator layer obtained via a multiple spike rapid thermal oxidation (RTO) procedure, and obtained via formation of an overlying conductive gate structure formed without the use of RIE procedures, preventing plasma induced damage of the gate insulator layer, is described. A composite insulator layer comprised of an underlying pad silicon oxide layer and an overlying silicon nitride layer, is formed on the surface of a semiconductor substrate, or on a semiconductor alloy layer located on the semiconductor substrate. A composite insulator shape is defined on the surface of the semiconductor alloy layer followed by formation of a SDE region in an area of the semiconductor alloy layer not covered by the composite insulator shape. Insulator spacers are formed on the sides of the composite insulator shape followed by formation of a heavily doped source/drain region in an area of the semiconductor alloy layer not covered by the composite insulator shape or by the insulator spacers. Deposition of an undoped silica glass (USG) layer, and planarization procedures, are followed by selective removal of the composite insulator shape, resulting in an opening in the USG layer, and in the adjacent insulator spacers, exposing a portion of the top surface of the semiconductor alloy layer located between portions of the SDE region. A gate insulator layer is formed on the exposed portion of the semiconductor alloy layer via a first portion of the spike RTO procedure, performed at a temperature which does not result in diffusion of SDE dopants but results in the growth of the gate insulator layer, while a second portion of the multiple spike RTO procedure, performed at a higher temperature results in activation of the dopants in both SDE and heavily doped source/drain regions. If desired an additional high dielectric constant insulator layer can be formed on the underlying gate insulator layer. Deposition of a conductive layer followed by a plananzation procedure results in a conductive gate structure on the underlying gate insulator layer, and located in the opening previously defined in the USG-insulator spacers.